ELECTRONICS - [counter device] - [page 2/3]
2. SCHEMATIC DESIGN
:: 2.1 Power Supply
The power supply provides a 12VDC stable voltage to the counter circuit. The 230V alternating
current (AC) is transformed, using a transformer with an output voltage of at least 12VAC.
This transformed AC voltage is rectified by the diodes D1 ... D4. Capacitor C1 removes most
ripples; the remaining ripple is added to the 7812. This component delivers a 12VDC stable
voltage. To protect the 7812 from heat, you may want to cool it using a heat sink. Capacitors
C2 and C3 removes high frequency components.
:: 2.2 Control Logic
The control logic is the most important part of the design. It decides when the input voltage
can be considered as "1" or as "0". This input voltage is applied to opto coupler 4N27. (This is
done to protect the circuit against a wrong use). If the input of the opto coupler is above a
certain voltage, the output of the NAND gate 1 will be "1". NAND2 and NAND3 are working together
as an AND gate. The 100 Hz blockwave signal is only passed to the output, if output of NAND gate 1
is "1". (NAND gate 4 is not used, but is applied to the ground. CMOS shouldn't have floating gates).
The 100Hz signal is used as time base, every pulse corresponds with 1/100 second. It's important to have a stable 100 Hz signal. (I decided to use the Velleman Crystal Timebase Kit for this). This signal may only be passed to the counters, if the "Enable" input is high. (1.5 ... 20 V).
:: 2.3 10-divider circuit
If the input condition is fulfilled (voltage at enable pins > 1.5 VDC), the displays must start
counting. In this case, the 100 Hz block wave signal is applied to the input of the counters.
I first made a 10-divider circuit, to transform the 100Hz signal into a 10Hz signal. This
decreases the precision of the counter, but I didn't have enough displays available for a
6-digit counter. The divider is created, using a CD4017 counter IC. The 100Hz signal is applied
to the input, and a 10Hz signal appears at the "Carry-Out" output. (The reset must be "0" to
count).
:: 3.4 5-digit counter
Disp1 to Disp5 indicates the time, in seconds. (Display1 is the least significant Digit, Display4
is the most significant Digit). The displays are 7-segment displays, with a common cathode. The
7 segments are numbered from a to g, while the decimal point is indicated with DP.
The displays are controlled using the CD4026's IC's. Those are counter IC's, and able to drive the
displays directly. Each "carry-out" output of a 4026, is connected to the frequency input of
the next 4026. This means every 4026 works as an 10-divider. (Disp1 counts at 10 Hz, Disp2
counts at 1 Hz, Disp3 counts at 1/10 Hz, Disp4 Counts at 1/100 Hz, Disp5 counts at 1/1000 Hz).
During every clock pulse, the internal counter increases, and shows the decimal value on the
display: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ... 0 ..
:: 3.5 Complete Schematics
The complete diagram can be downloaded from this site.
